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| author | Peter Maydell | 2016-06-17 16:23:47 +0200 |
|---|---|---|
| committer | Peter Maydell | 2016-06-17 16:23:51 +0200 |
| commit | 359fbe65e01e13f582d3b9103e7c3ec5ac367a18 (patch) | |
| tree | 5dc875f829bcdb3e3aab7480542a0ebe9e41b98b /cputlb.c | |
| parent | hw/intc/arm_gicv3: Implement gicv3_set_irq() (diff) | |
| download | qemu-359fbe65e01e13f582d3b9103e7c3ec5ac367a18.tar.gz qemu-359fbe65e01e13f582d3b9103e7c3ec5ac367a18.tar.xz qemu-359fbe65e01e13f582d3b9103e7c3ec5ac367a18.zip | |
hw/intc/arm_gicv3: Implement GICv3 CPU interface registers
Implement the CPU interface registers for the GICv3; these are
CPU system registers, not MMIO registers.
This commit implements all the registers which are simple
accessors for GIC state, but not those which act as interfaces
for acknowledging, dismissing or generating interrupts. (Those
will be added in a later commit.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-16-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'cputlb.c')
0 files changed, 0 insertions, 0 deletions