diff options
author | Michael Clark | 2018-03-02 13:31:10 +0100 |
---|---|---|
committer | Michael Clark | 2018-03-06 20:30:28 +0100 |
commit | ea10325917c8a8f92611025c85950c00f826cb73 (patch) | |
tree | 4e3a4be4f06dee5e42d712f948f336cbf4f7979b /disas.c | |
parent | RISC-V CPU Core Definition (diff) | |
download | qemu-ea10325917c8a8f92611025c85950c00f826cb73.tar.gz qemu-ea10325917c8a8f92611025c85950c00f826cb73.tar.xz qemu-ea10325917c8a8f92611025c85950c00f826cb73.zip |
RISC-V Disassembler
The RISC-V disassembler has no dependencies outside of the 'disas'
directory so it can be applied independently. The majority of the
disassembler is machine-generated from instruction set metadata:
- https://github.com/michaeljclark/riscv-meta
Expected checkpatch errors for consistency and brevity reasons:
ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: space prohibited between function name and open parenthesis '('
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'disas.c')
-rw-r--r-- | disas.c | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -522,6 +522,8 @@ void disas(FILE *out, void *code, unsigned long size) # ifdef _ARCH_PPC64 s.info.cap_mode = CS_MODE_64; # endif +#elif defined(__riscv__) + print_insn = print_insn_riscv; #elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS) print_insn = print_insn_arm_a64; s.info.cap_arch = CS_ARCH_ARM64; |