diff options
| author | Peter Maydell | 2018-06-15 15:57:14 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-06-15 16:23:34 +0200 |
| commit | f81804a52b5d4609f68ea367a55a2ccb4cc99f77 (patch) | |
| tree | 7fd073b56b67ac6edf5e330ace0c05858884553c /disas/xtensa.c | |
| parent | arm: Don't crash if user tries to use a Cortex-M CPU without an NVIC (diff) | |
| download | qemu-f81804a52b5d4609f68ea367a55a2ccb4cc99f77.tar.gz qemu-f81804a52b5d4609f68ea367a55a2ccb4cc99f77.tar.xz qemu-f81804a52b5d4609f68ea367a55a2ccb4cc99f77.zip | |
hw/core/or-irq: Support more than 16 inputs to an OR gate
For the IoTKit MPC support, we need to wire together the
interrupt outputs of 17 MPCs; this exceeds the current
value of MAX_OR_LINES. Increase MAX_OR_LINES to 32 (which
should be enough for anyone).
The tricky part is retaining the migration compatibility for
existing OR gates; we add a subsection which is only used
for larger OR gates, and define it such that we can freely
increase MAX_OR_LINES in future (or even move to a dynamically
allocated levels[] array without an upper size limit) without
breaking compatibility.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180604152941.20374-10-peter.maydell@linaro.org
Diffstat (limited to 'disas/xtensa.c')
0 files changed, 0 insertions, 0 deletions