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| author | Frédéric Pétrot | 2022-01-06 22:00:57 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-08 06:46:10 +0100 |
| commit | 332dab68785bba0381790fef94f4f433e8e806ea (patch) | |
| tree | c0e0521748bb4eb4eeba05e71ac458e4038ef977 /disas | |
| parent | target/riscv: array for the 64 upper bits of 128-bit registers (diff) | |
| download | qemu-332dab68785bba0381790fef94f4f433e8e806ea.tar.gz qemu-332dab68785bba0381790fef94f4f433e8e806ea.tar.xz qemu-332dab68785bba0381790fef94f4f433e8e806ea.zip | |
target/riscv: setup everything for rv64 to support rv128 execution
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr
[ Changed by AF
- Rename CPU to "x-rv128"
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'disas')
| -rw-r--r-- | disas/riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/disas/riscv.c b/disas/riscv.c index 793ad14c27..03c8dc9961 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -3090,3 +3090,8 @@ int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info) { return print_insn_riscv(memaddr, info, rv64); } + +int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) +{ + return print_insn_riscv(memaddr, info, rv128); +} |