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authorLeon Alrae2014-06-27 09:49:04 +0200
committerLeon Alrae2014-10-13 13:38:25 +0200
commit4267d3e6e0d7be184ef343919640e7be6ae34e71 (patch)
tree79c4dbf16dad5ae83cde3f6fb530670526788708 /disas
parenttarget-mips: redefine Integer Multiply and Divide instructions (diff)
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target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6
Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping with MIPS32R6 SDBBP. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'disas')
-rw-r--r--disas/mips.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/disas/mips.c b/disas/mips.c
index 16cb2acd81..8ee8758e50 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -1217,6 +1217,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, membership */
+{"clz", "U,s", 0x00000050, 0xfc1f07ff, WR_d|RD_s, 0, I32R6},
+{"clo", "U,s", 0x00000051, 0xfc1f07ff, WR_d|RD_s, 0, I32R6},
+{"dclz", "U,s", 0x00000052, 0xfc1f07ff, WR_d|RD_s, 0, I64R6},
+{"dclo", "U,s", 0x00000053, 0xfc1f07ff, WR_d|RD_s, 0, I64R6},
+{"sdbbp", "B", 0x0000000e, 0xfc00003f, TRAP, 0, I32R6},
{"mul", "d,s,t", 0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
{"muh", "d,s,t", 0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
{"mulu", "d,s,t", 0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},