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| author | Anup Patel | 2022-06-30 08:11:50 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-09-07 09:18:32 +0200 |
| commit | 9a1f054d5bd9acaa82b66e09309482cba9eced63 (patch) | |
| tree | 22c056a7fb1602b2a2cbf498e210ba5fcedba68d /disas | |
| parent | target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() (diff) | |
| download | qemu-9a1f054d5bd9acaa82b66e09309482cba9eced63.tar.gz qemu-9a1f054d5bd9acaa82b66e09309482cba9eced63.tar.xz qemu-9a1f054d5bd9acaa82b66e09309482cba9eced63.zip | |
target/riscv: Force disable extensions if priv spec version does not match
We should disable extensions in riscv_cpu_realize() if minimum required
priv spec version is not satisfied. This also ensures that machines with
priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
extensions.
Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the device tree")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Message-Id: <20220630061150.905174-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'disas')
0 files changed, 0 insertions, 0 deletions