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authorCédric Le Goater2020-12-10 12:11:03 +0100
committerCédric Le Goater2020-12-10 12:11:03 +0100
commitaf453a5ef58d21fa902aea9b6e4bc2312ac0467f (patch)
tree95f431d386a1e038288e2c8a3e536ead192b7986 /docs/devel/build-system.rst
parentast2600: SRAM is 89KB (diff)
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aspeed/smc: Add support for address lane disablement
The controller can be configured to disable or enable address and data byte lanes when issuing commands. This is useful in read command mode to send SPI NOR commands that don't have an address space, such as RDID. It's a good way to have a unified read operation for registers and flash contents accesses. A new SPI driver proposed by Aspeed makes use of this feature. Add support for address lanes to start with. We will do the same for the data lanes if they are controlled one day. Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20201120161547.740806-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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