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author | Peter Maydell | 2020-02-14 18:50:57 +0100 |
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committer | Peter Maydell | 2020-02-21 17:07:00 +0100 |
commit | f8af1143ef93954e77cf59e09b5e004dafbd64fd (patch) | |
tree | 62332563a07d2de02d5f146e60e5508d37dfcb82 /docs/pcie_pci_bridge.txt | |
parent | target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers (diff) | |
download | qemu-f8af1143ef93954e77cf59e09b5e004dafbd64fd.tar.gz qemu-f8af1143ef93954e77cf59e09b5e004dafbd64fd.tar.xz qemu-f8af1143ef93954e77cf59e09b5e004dafbd64fd.zip |
target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan
In take_aarch32_exception(), we know we are dealing with a CPU that
has AArch32, so the right isar_feature test is aa32_pan, not aa64_pan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-3-peter.maydell@linaro.org
Diffstat (limited to 'docs/pcie_pci_bridge.txt')
0 files changed, 0 insertions, 0 deletions