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| author | Daniel P. Berrangé | 2019-05-15 16:10:11 +0200 |
|---|---|---|
| committer | Eduardo Habkost | 2019-05-21 20:39:05 +0200 |
| commit | 2c7e82a30774730100da9dbe68d2360459030d91 (patch) | |
| tree | 5fe04d7250a9597b9e2fe0555a600769424cb753 /docs/qemu-cpu-models.texi | |
| parent | target/i386: define md-clear bit (diff) | |
| download | qemu-2c7e82a30774730100da9dbe68d2360459030d91.tar.gz qemu-2c7e82a30774730100da9dbe68d2360459030d91.tar.xz qemu-2c7e82a30774730100da9dbe68d2360459030d91.zip | |
docs: recommend use of md-clear feature on all Intel CPUs
Update x86 CPU model guidance to recommend that the md-clear feature is
manually enabled with all Intel CPU models, when supported by the host
microcode.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20190515141011.5315-3-berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'docs/qemu-cpu-models.texi')
| -rw-r--r-- | docs/qemu-cpu-models.texi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/docs/qemu-cpu-models.texi b/docs/qemu-cpu-models.texi index 23c11dc86f..ad040cfc98 100644 --- a/docs/qemu-cpu-models.texi +++ b/docs/qemu-cpu-models.texi @@ -200,6 +200,18 @@ Not included by default in any Intel CPU model. Should be explicitly turned on for all Intel CPU models. Note that not all CPU hardware will support this feature. + +@item @code{md-clear} + +Required to confirm the MDS (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, +CVE-2019-11091) fixes. + +Not included by default in any Intel CPU model. + +Must be explicitly turned on for all Intel CPU models. + +Requires the host CPU microcode to support this feature before it +can be used for guest CPUs. @end table |