diff options
| author | Richard Henderson | 2022-03-01 22:59:48 +0100 |
|---|---|---|
| committer | Peter Maydell | 2022-03-02 20:27:37 +0100 |
| commit | 777ab8d84442dd6c0c5fbf787de87779d5ab82e8 (patch) | |
| tree | 5fd24e221ad8c56addbcc50e38a8f402eddee39f /docs/specs | |
| parent | target/arm: Honor TCR_ELx.{I}PS (diff) | |
| download | qemu-777ab8d84442dd6c0c5fbf787de87779d5ab82e8.tar.gz qemu-777ab8d84442dd6c0c5fbf787de87779d5ab82e8.tar.xz qemu-777ab8d84442dd6c0c5fbf787de87779d5ab82e8.zip | |
target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
The original A.a revision of the AArch64 ARM required that we
force-extend the addresses in these registers from 49 bits.
This language has been loosened via a combination of IMPLEMENTATION
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
the entire aligned address.
This means that we do not have to consider whether or not FEAT_LVA
is enabled, and decide from which bit an address might need to be
extended.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs/specs')
0 files changed, 0 insertions, 0 deletions