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| author | Richard Henderson | 2022-06-20 19:52:01 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-06-27 12:18:17 +0200 |
| commit | e74c097638d38b46d9c68f11565432034afc0ad0 (patch) | |
| tree | 8f885e504469e1bc251308e66fb0592c4d395868 /docs/system/cpu-models-mips.rst.inc | |
| parent | target/arm: Unexport aarch64_add_*_properties (diff) | |
| download | qemu-e74c097638d38b46d9c68f11565432034afc0ad0.tar.gz qemu-e74c097638d38b46d9c68f11565432034afc0ad0.tar.xz qemu-e74c097638d38b46d9c68f11565432034afc0ad0.zip | |
target/arm: Add cpu properties for SME
Mirror the properties for SVE. The main difference is
that any arbitrary set of powers of 2 may be supported,
and not the stricter constraints that apply to SVE.
Include a property to control FEAT_SME_FA64, as failing
to restrict the runtime to the proper subset of insns
could be a major point for bugs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220620175235.60881-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs/system/cpu-models-mips.rst.inc')
0 files changed, 0 insertions, 0 deletions