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| author | Stafford Horne | 2022-07-01 01:29:17 +0200 |
|---|---|---|
| committer | Stafford Horne | 2022-09-04 08:02:57 +0200 |
| commit | b14df228d7c4fe6e86e7f8a4998e9ccf4967b678 (patch) | |
| tree | 1e7235fb2cae6d8fa14dc8e4d9ff27b04de03fae /docs/system/openrisc/cpu-features.rst | |
| parent | hw/openrisc: virt: pass random seed to fdt (diff) | |
| download | qemu-b14df228d7c4fe6e86e7f8a4998e9ccf4967b678.tar.gz qemu-b14df228d7c4fe6e86e7f8a4998e9ccf4967b678.tar.xz qemu-b14df228d7c4fe6e86e7f8a4998e9ccf4967b678.zip | |
docs/system: openrisc: Add OpenRISC documentation
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'docs/system/openrisc/cpu-features.rst')
| -rw-r--r-- | docs/system/openrisc/cpu-features.rst | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/docs/system/openrisc/cpu-features.rst b/docs/system/openrisc/cpu-features.rst new file mode 100644 index 0000000000..aeb65e22ff --- /dev/null +++ b/docs/system/openrisc/cpu-features.rst @@ -0,0 +1,15 @@ +CPU Features +============ + +The QEMU emulation of the OpenRISC architecture provides following built in +features. + +- Shadow GPRs +- MMU TLB with 128 entries, 1 way +- Power Management (PM) +- Programmable Interrupt Controller (PIC) +- Tick Timer + +These features are on by default and the presence can be confirmed by checking +the contents of the Unit Presence Register (``UPR``) and CPU Configuration +Register (``CPUCFGR``). |