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| author | Peter Maydell | 2020-10-19 11:52:56 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-10-19 11:52:57 +0200 |
| commit | 22d30b340aa5d8a2b1fbc90d5263f801f1584d01 (patch) | |
| tree | de271aafb22a72bd5ccecf151e463c29b4b00524 /docs/system | |
| parent | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ... (diff) | |
| parent | target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64) (diff) | |
| download | qemu-22d30b340aa5d8a2b1fbc90d5263f801f1584d01.tar.gz qemu-22d30b340aa5d8a2b1fbc90d5263f801f1584d01.tar.xz qemu-22d30b340aa5d8a2b1fbc90d5263f801f1584d01.zip | |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-next-20201017' into staging
MIPS patches queue
. Fix some comment spelling errors
. Demacro some TCG helpers
. Add loongson-ext lswc2/lsdc2 group of instructions
. Log unimplemented cache opcode
. Increase number of TLB entries on the 34Kf core
. Allow the CPU to use dynamic frequencies
. Calculate the CP0 timer period using the CPU frequency
. Set CPU frequency for each machine
. Fix Malta FPGA I/O region size
. Allow running qtests when ROM is missing
. Add record/replay acceptance tests
. Update MIPS CPU documentation
. MAINTAINERS updates
CI jobs results:
https://gitlab.com/philmd/qemu/-/pipelines/203931842
https://travis-ci.org/github/philmd/qemu/builds/736491461
https://cirrus-ci.com/build/6272264062631936
https://app.shippable.com/github/philmd/qemu/runs/886/summary/console
# gpg: Signature made Sat 17 Oct 2020 14:59:53 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/mips-next-20201017: (44 commits)
target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)
MAINTAINERS: Remove duplicated Malta test entries
MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mail
MAINTAINERS: Put myself forward for MIPS target
MAINTAINERS: Remove myself
docs/system: Update MIPS CPU documentation
tests/acceptance: Add MIPS record/replay tests
hw/mips: Remove exit(1) in case of missing ROM
hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON
hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)
hw/mips: Simplify loading 64-bit ELF kernels
hw/mips/malta: Use clearer qdev style
hw/mips/malta: Move gt64120 related code together
hw/mips/malta: Fix FPGA I/O region size
target/mips/cpu: Display warning when CPU is used without input clock
hw/mips/cps: Do not allow use without input clock
hw/mips/malta: Set CPU frequency to 320 MHz
hw/mips/boston: Set CPU frequency to 1 GHz
hw/mips/cps: Expose input clock and connect it to CPU cores
hw/mips/jazz: Correct CPU frequencies
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'docs/system')
| -rw-r--r-- | docs/system/cpu-models-mips.rst.inc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/docs/system/cpu-models-mips.rst.inc b/docs/system/cpu-models-mips.rst.inc index 499b5b6fed..02cc4bb884 100644 --- a/docs/system/cpu-models-mips.rst.inc +++ b/docs/system/cpu-models-mips.rst.inc @@ -48,11 +48,17 @@ across all desired hosts. ``I6400`` MIPS64 Processor (Release 6, 2014) +``Loongson-2E`` + MIPS64 Processor (Loongson 2, 2006) + ``Loongson-2F`` MIPS64 Processor (Loongson 2, 2008) -``Loongson-2E`` - MIPS64 Processor (Loongson 2, 2006) +``Loongson-3A1000`` + MIPS64 Processor (Loongson 3, 2010) + +``Loongson-3A4000`` + MIPS64 Processor (Loongson 3, 2018) ``mips64dspr2`` MIPS64 Processor (Release 2, 2006) |