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| author | Cédric Le Goater | 2021-03-09 12:01:28 +0100 |
|---|---|---|
| committer | Cédric Le Goater | 2021-03-09 12:01:28 +0100 |
| commit | 2ecf17264debe1bc3399fe587690c78d03e8401b (patch) | |
| tree | 792d6d3331647aff8e0d1e5a587b240bcb0d19dc /docs/system | |
| parent | hw/arm: ast2600: Correct the iBT interrupt ID (diff) | |
| download | qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.tar.gz qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.tar.xz qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.zip | |
hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'docs/system')
| -rw-r--r-- | docs/system/arm/aspeed.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 8972aa3f7b..d1fb8f25b3 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -48,6 +48,7 @@ Supported devices * UART * Ethernet controllers * Front LEDs (PCA9552 on I2C bus) + * LPC Peripheral Controller (a subset of subdevices are supported) Missing devices @@ -56,7 +57,6 @@ Missing devices * Coprocessor support * ADC (out of tree implementation) * PWM and Fan Controller - * LPC Bus Controller * Slave GPIO Controller * Super I/O Controller * Hash/Crypto Engine |