diff options
| author | Peter Maydell | 2021-05-04 14:09:11 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-05-10 18:21:54 +0200 |
| commit | 5bddf92e689c0a3da57f4fd17b83d4eb1e436b80 (patch) | |
| tree | b7c25948f690e9d2b97298874a22159167e156f0 /docs/system | |
| parent | hw/misc/mps2-scc: Add "QEMU interface" comment (diff) | |
| download | qemu-5bddf92e689c0a3da57f4fd17b83d4eb1e436b80.tar.gz qemu-5bddf92e689c0a3da57f4fd17b83d4eb1e436b80.tar.xz qemu-5bddf92e689c0a3da57f4fd17b83d4eb1e436b80.zip | |
hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping
On some boards, SCC config register CFG0 bit 0 controls whether
parts of the board memory map are remapped. Support this with:
* a device property scc-cfg0 so the board can specify the
initial value of the CFG0 register
* an outbound GPIO line which tracks bit 0 and which the board
can wire up to provide the remapping
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210504120912.23094-3-peter.maydell@linaro.org
Diffstat (limited to 'docs/system')
0 files changed, 0 insertions, 0 deletions