diff options
| author | Bin Meng | 2021-06-27 16:28:15 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-07-15 00:56:00 +0200 |
| commit | d3745751009bc7c56741ea04c4d3ca5619f845f2 (patch) | |
| tree | 1b44f8d2302008547c858036b4aa864d851bd6cc /docs/system | |
| parent | target/riscv: csr: Remove redundant check in fp csr read/write routines (diff) | |
| download | qemu-d3745751009bc7c56741ea04c4d3ca5619f845f2.tar.gz qemu-d3745751009bc7c56741ea04c4d3ca5619f845f2.tar.xz qemu-d3745751009bc7c56741ea04c4d3ca5619f845f2.zip | |
docs/system: riscv: Fix CLINT name in the sifive_u doc
It's Core *Local* Interruptor, not 'Level'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627142816.19789-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'docs/system')
| -rw-r--r-- | docs/system/riscv/sifive_u.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst index 32d0a1b85d..01108b5ecc 100644 --- a/docs/system/riscv/sifive_u.rst +++ b/docs/system/riscv/sifive_u.rst @@ -11,7 +11,7 @@ The ``sifive_u`` machine supports the following devices: * 1 E51 / E31 core * Up to 4 U54 / U34 cores -* Core Level Interruptor (CLINT) +* Core Local Interruptor (CLINT) * Platform-Level Interrupt Controller (PLIC) * Power, Reset, Clock, Interrupt (PRCI) * L2 Loosely Integrated Memory (L2-LIM) |