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| author | James Hogan | 2016-04-01 16:49:39 +0200 |
|---|---|---|
| committer | Richard Henderson | 2016-04-05 21:47:47 +0200 |
| commit | 2dc7553d0c0a3915c649e1a91b0f0be70b4674b3 (patch) | |
| tree | 285c42ff321f2be9255adfa7d34717db3a04ad16 /docs | |
| parent | bsd-user: Suppress gcc 4.x -Wpointer-sign (included in -Wall) warning (diff) | |
| download | qemu-2dc7553d0c0a3915c649e1a91b0f0be70b4674b3.tar.gz qemu-2dc7553d0c0a3915c649e1a91b0f0be70b4674b3.tar.xz qemu-2dc7553d0c0a3915c649e1a91b0f0be70b4674b3.zip | |
tcg/mips: Fix type of tcg_target_reg_alloc_order[]
The MIPS TCG backend is the only one to have
tcg_target_reg_alloc_order[] elements of type TCGReg rather than int.
This resulted in commit 91478cefaaf2 ("tcg: Allocate indirect_base
temporaries in a different order") breaking the build on MIPS since the
type differed from indirect_reg_alloc_order[]:
tcg/tcg.c:1725:44: error: pointer type mismatch in conditional expression [-Werror]
order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order;
^
Make it an array of ints to fix the build and match other architectures.
Fixes: 91478cefaaf2 ("tcg: Allocate indirect_base temporaries in a different order")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Message-Id: <1459522179-6584-1-git-send-email-james.hogan@imgtec.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'docs')
0 files changed, 0 insertions, 0 deletions