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| author | Philippe Mathieu-Daudé | 2020-12-14 01:32:12 +0100 |
|---|---|---|
| committer | Laurent Vivier | 2020-12-17 10:34:59 +0100 |
| commit | 388765a05bde86de9d9b66348afed6551c58f091 (patch) | |
| tree | 899871a522f0ccdb60a047667c348491e06df027 /docs | |
| parent | linux-user/elfload: Rename MIPS GET_FEATURE() as GET_FEATURE_INSN() (diff) | |
| download | qemu-388765a05bde86de9d9b66348afed6551c58f091.tar.gz qemu-388765a05bde86de9d9b66348afed6551c58f091.tar.xz qemu-388765a05bde86de9d9b66348afed6551c58f091.zip | |
linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro
ISA features are usually denoted in read-only bits from
CPU registers. Add the GET_FEATURE_REG_SET() macro which
checks if a CPU register has bits set.
Use the macro to check for MSA (which sets the MSAP bit of
the Config3 register when the ASE implementation is present).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214003215.344522-4-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'docs')
0 files changed, 0 insertions, 0 deletions