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authorHuacai Chen2020-10-07 10:39:35 +0200
committerPhilippe Mathieu-Daudé2020-10-17 13:59:40 +0200
commitb5330cf19ad29a71c3981d315a14f17db539ec80 (patch)
treee98df06b05b1f71421345cc8b2c8d53653bfc7b5 /docs
parenttests/acceptance: Add MIPS record/replay tests (diff)
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docs/system: Update MIPS CPU documentation
Add Loongson-3A CPU models description. Signed-off-by: Huacai Chen <chenhc@lemote.com> Message-Id: <1602059975-10115-10-git-send-email-chenhc@lemote.com> [PMD: Split patch in 2: CPU / machine] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'docs')
-rw-r--r--docs/system/cpu-models-mips.rst.inc10
1 files changed, 8 insertions, 2 deletions
diff --git a/docs/system/cpu-models-mips.rst.inc b/docs/system/cpu-models-mips.rst.inc
index 499b5b6fed..02cc4bb884 100644
--- a/docs/system/cpu-models-mips.rst.inc
+++ b/docs/system/cpu-models-mips.rst.inc
@@ -48,11 +48,17 @@ across all desired hosts.
``I6400``
MIPS64 Processor (Release 6, 2014)
+``Loongson-2E``
+ MIPS64 Processor (Loongson 2, 2006)
+
``Loongson-2F``
MIPS64 Processor (Loongson 2, 2008)
-``Loongson-2E``
- MIPS64 Processor (Loongson 2, 2006)
+``Loongson-3A1000``
+ MIPS64 Processor (Loongson 3, 2010)
+
+``Loongson-3A4000``
+ MIPS64 Processor (Loongson 3, 2018)
``mips64dspr2``
MIPS64 Processor (Release 2, 2006)