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| author | Peter Maydell | 2022-08-19 13:00:50 +0200 |
|---|---|---|
| committer | Richard Henderson | 2022-09-14 12:19:40 +0200 |
| commit | d22c564958ffa6bd40be34c6ea3333ee7ef73b68 (patch) | |
| tree | 82fe84cb258311ae6eefd828ec76c145321df7ca /docs | |
| parent | target/arm: Implement ID_MMFR5 (diff) | |
| download | qemu-d22c564958ffa6bd40be34c6ea3333ee7ef73b68.tar.gz qemu-d22c564958ffa6bd40be34c6ea3333ee7ef73b68.tar.xz qemu-d22c564958ffa6bd40be34c6ea3333ee7ef73b68.zip | |
target/arm: Implement ID_DFR1
In Armv8.6, a new AArch32 ID register ID_DFR1 is defined; implement
it. We don't have any CPUs with features that they need to advertise
here yet, but plumbing in the ID register gives it the right name
when debugging and will help in future when we do add a CPU that
has non-zero ID_DFR1 fields.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220819110052.2942289-5-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'docs')
0 files changed, 0 insertions, 0 deletions