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| author | Alistair Francis | 2021-09-09 05:55:15 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-09-20 23:56:49 +0200 |
| commit | ea6eaa0604d2ad66636f968842fe9ff315b065c8 (patch) | |
| tree | d88d85bfc03c7f7dd642d39a624f4da682535c3c /docs | |
| parent | hw/timer: Add SiFive PWM support (diff) | |
| download | qemu-ea6eaa0604d2ad66636f968842fe9ff315b065c8.tar.gz qemu-ea6eaa0604d2ad66636f968842fe9ff315b065c8.tar.xz qemu-ea6eaa0604d2ad66636f968842fe9ff315b065c8.zip | |
sifive_u: Connect the SiFive PWM device
Connect the SiFive PWM device and expose it via the device tree.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.francis@wdc.com
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/system/riscv/sifive_u.rst | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst index 01108b5ecc..7c65e9c440 100644 --- a/docs/system/riscv/sifive_u.rst +++ b/docs/system/riscv/sifive_u.rst @@ -24,6 +24,7 @@ The ``sifive_u`` machine supports the following devices: * 2 QSPI controllers * 1 ISSI 25WP256 flash * 1 SD card in SPI mode +* PWM0 and PWM1 Please note the real world HiFive Unleashed board has a fixed configuration of 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode. |