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| author | Damien Hedde | 2020-04-06 15:52:48 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-04-30 16:35:41 +0200 |
| commit | 38867cb7ec90253289cab22c13282a3ef6530f69 (patch) | |
| tree | f0a5967577182bbbbd91916f38f3e6ef07ffb68b /exec.c | |
| parent | docs/clocks: add device's clock documentation (diff) | |
| download | qemu-38867cb7ec90253289cab22c13282a3ef6530f69.tar.gz qemu-38867cb7ec90253289cab22c13282a3ef6530f69.tar.xz qemu-38867cb7ec90253289cab22c13282a3ef6530f69.zip | |
hw/misc/zynq_slcr: add clock generation for uarts
Add some clocks to zynq_slcr
+ the main input clock (ps_clk)
+ the reference clock outputs for each uart (uart0 & 1)
This commit also transitional the slcr to multi-phase reset as it is
required to initialize the clocks correctly.
The clock frequencies are computed using the internal pll & uart configuration
registers and the input ps_clk frequency.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200406135251.157596-7-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'exec.c')
0 files changed, 0 insertions, 0 deletions