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| author | Richard Henderson | 2020-03-05 17:09:18 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-03-05 17:09:18 +0100 |
| commit | 1bed4d2e55459129c19f5952bcfc65bd0c70db5b (patch) | |
| tree | 1ca024c80d1c9bc9bc113b70d0053ab129f1956f /fpu | |
| parent | target/arm: Honor the HCR_EL2.TACR bit (diff) | |
| download | qemu-1bed4d2e55459129c19f5952bcfc65bd0c70db5b.tar.gz qemu-1bed4d2e55459129c19f5952bcfc65bd0c70db5b.tar.xz qemu-1bed4d2e55459129c19f5952bcfc65bd0c70db5b.zip | |
target/arm: Honor the HCR_EL2.TPCP bit
This bit traps EL1 access to cache maintenance insns that operate
to the point of coherency or persistence.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'fpu')
0 files changed, 0 insertions, 0 deletions