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| author | Richard Henderson | 2018-08-16 15:05:29 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-16 15:29:58 +0200 |
| commit | b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b (patch) | |
| tree | 4bc506b48e861e58a2d406a1ff6125abd0b7c7ec /fpu | |
| parent | target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half (diff) | |
| download | qemu-b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b.tar.gz qemu-b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b.tar.xz qemu-b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b.zip | |
target/arm: Fix aa64 FCADD and FCMLA decode
These insns require u=1; failed to include that in the switch
cases. This probably happened during one of the rebases just
before final commit.
Fixes: d17b7cdcf4e
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180810193129.1556-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'fpu')
0 files changed, 0 insertions, 0 deletions