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| author | Michael Clark | 2018-03-02 13:31:10 +0100 |
|---|---|---|
| committer | Michael Clark | 2018-03-06 20:30:28 +0100 |
| commit | f798f1e29be6066feafa2a88aa94441695339e0a (patch) | |
| tree | 2e4feef28a59143302f1eae0b5aed2c3e6993804 /fpu | |
| parent | RISC-V CPU Helpers (diff) | |
| download | qemu-f798f1e29be6066feafa2a88aa94441695339e0a.tar.gz qemu-f798f1e29be6066feafa2a88aa94441695339e0a.tar.xz qemu-f798f1e29be6066feafa2a88aa94441695339e0a.zip | |
RISC-V FPU Support
Helper routines for FPU instructions and NaN definitions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'fpu')
| -rw-r--r-- | fpu/softfloat-specialize.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 9ccb59422c..27834af0de 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -114,7 +114,8 @@ float32 float32_default_nan(float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) return const_float32(0x7FFFFFFF); #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ - defined(TARGET_XTENSA) || defined(TARGET_S390X) || defined(TARGET_TRICORE) + defined(TARGET_XTENSA) || defined(TARGET_S390X) || \ + defined(TARGET_TRICORE) || defined(TARGET_RISCV) return const_float32(0x7FC00000); #elif defined(TARGET_HPPA) return const_float32(0x7FA00000); @@ -139,7 +140,7 @@ float64 float64_default_nan(float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) return const_float64(LIT64(0x7FFFFFFFFFFFFFFF)); #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ - defined(TARGET_S390X) + defined(TARGET_S390X) || defined(TARGET_RISCV) return const_float64(LIT64(0x7FF8000000000000)); #elif defined(TARGET_HPPA) return const_float64(LIT64(0x7FF4000000000000)); @@ -203,7 +204,7 @@ float128 float128_default_nan(float_status *status) r.high = LIT64(0x7FFF7FFFFFFFFFFF); } else { r.low = LIT64(0x0000000000000000); -#if defined(TARGET_S390X) || defined(TARGET_PPC) +#if defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_RISCV) r.high = LIT64(0x7FFF800000000000); #else r.high = LIT64(0xFFFF800000000000); |