diff options
| author | Richard Henderson | 2020-03-05 17:09:18 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-03-05 17:09:18 +0100 |
| commit | 38262d8a732f8bd0e9ca3dc064f6e73d00c08b9a (patch) | |
| tree | 9ae03ff18a901b5d1897d4d2beefad2d4e430c9a /gdb-xml/riscv-64bit-csr.xml | |
| parent | target/arm: Honor the HCR_EL2.TPCP bit (diff) | |
| download | qemu-38262d8a732f8bd0e9ca3dc064f6e73d00c08b9a.tar.gz qemu-38262d8a732f8bd0e9ca3dc064f6e73d00c08b9a.tar.xz qemu-38262d8a732f8bd0e9ca3dc064f6e73d00c08b9a.zip | |
target/arm: Honor the HCR_EL2.TPU bit
This bit traps EL1 access to cache maintenance insns that operate
to the point of unification. There are no longer any references to
plain aa64_cacheop_access, so remove it.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'gdb-xml/riscv-64bit-csr.xml')
0 files changed, 0 insertions, 0 deletions