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| author | Andrew Burgess | 2022-08-31 10:41:22 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-09-26 23:04:38 +0200 |
| commit | 94452ac4cf263e8996613db8d981e4ea85bd019a (patch) | |
| tree | 01ef34d152c9c459a34a28a3e2e688551bffde6a /gdb-xml | |
| parent | target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} (diff) | |
| download | qemu-94452ac4cf263e8996613db8d981e4ea85bd019a.tar.gz qemu-94452ac4cf263e8996613db8d981e4ea85bd019a.tar.xz qemu-94452ac4cf263e8996613db8d981e4ea85bd019a.zip | |
target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml
While testing some changes to GDB's handling for the RISC-V registers
fcsr, fflags, and frm, I spotted that QEMU includes these registers
twice in the target description it sends to GDB, once in the fpu
feature, and once in the csr feature.
Right now things basically work OK, QEMU maps these registers onto two
different register numbers, e.g. fcsr maps to both 68 and 73, and GDB
can use either of these to access the register.
However, GDB's target descriptions don't really work this way, each
register should appear just once in a target description, mapping the
register name onto the number GDB should use when accessing the
register on the target. Duplicate register names actually result in
duplicate registers on the GDB side, however, as the registers have
the same name, the user can only access one of these registers.
Currently GDB has a hack in place, specifically for RISC-V, to spot
the duplicate copies of these three registers, and hide them from the
user, ensuring the user only ever sees a single copy of each.
In this commit I propose fixing this issue on the QEMU side, and in
the process, simplify the fpu register handling a little.
I think we should, remove fflags, frm, and fcsr from the two (32-bit
and 64-bit) fpu feature xml files. These files will only contain the
32 core floating point register f0 to f31. The fflags, frm, and fcsr
registers will continue to be advertised in the csr feature as they
currently are.
With that change made, I will simplify riscv_gdb_get_fpu and
riscv_gdb_set_fpu, removing the extra handling for the 3 status
registers.
Signed-off-by: Andrew Burgess <aburgess@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <0fbf2a5b12e3210ff3867d5cf7022b3f3462c9c8.1661934573.git.aburgess@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'gdb-xml')
| -rw-r--r-- | gdb-xml/riscv-32bit-fpu.xml | 4 | ||||
| -rw-r--r-- | gdb-xml/riscv-64bit-fpu.xml | 4 |
2 files changed, 0 insertions, 8 deletions
diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml index 1eaae9119e..84a44ba8df 100644 --- a/gdb-xml/riscv-32bit-fpu.xml +++ b/gdb-xml/riscv-32bit-fpu.xml @@ -43,8 +43,4 @@ <reg name="ft9" bitsize="32" type="ieee_single"/> <reg name="ft10" bitsize="32" type="ieee_single"/> <reg name="ft11" bitsize="32" type="ieee_single"/> - - <reg name="fflags" bitsize="32" type="int" regnum="66"/> - <reg name="frm" bitsize="32" type="int" regnum="67"/> - <reg name="fcsr" bitsize="32" type="int" regnum="68"/> </feature> diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml index 794854cc01..9856a9d1d3 100644 --- a/gdb-xml/riscv-64bit-fpu.xml +++ b/gdb-xml/riscv-64bit-fpu.xml @@ -49,8 +49,4 @@ <reg name="ft9" bitsize="64" type="riscv_double"/> <reg name="ft10" bitsize="64" type="riscv_double"/> <reg name="ft11" bitsize="64" type="riscv_double"/> - - <reg name="fflags" bitsize="32" type="int" regnum="66"/> - <reg name="frm" bitsize="32" type="int" regnum="67"/> - <reg name="fcsr" bitsize="32" type="int" regnum="68"/> </feature> |