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| author | eopXD | 2022-05-05 11:42:17 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-05-24 01:48:20 +0200 |
| commit | 02b511985e33d71859943682860f629ead5bd20a (patch) | |
| tree | 51442a3b469355afd92d2abfc7d1fc093cb27c01 /hw/acpi/acpi-stub.c | |
| parent | target/riscv: Fix VS mode hypervisor CSR access (diff) | |
| download | qemu-02b511985e33d71859943682860f629ead5bd20a.tar.gz qemu-02b511985e33d71859943682860f629ead5bd20a.tar.xz qemu-02b511985e33d71859943682860f629ead5bd20a.zip | |
target/riscv: rvv: Fix early exit condition for whole register load/store
Vector whole register load instructions have EEW encoded in the opcode,
so we shouldn't take SEW here. Vector whole register store instructions
are always EEW=8.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165181414065.18540.14828125053334599921-0@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/acpi/acpi-stub.c')
0 files changed, 0 insertions, 0 deletions