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| author | Jiahui Cen | 2021-01-14 11:06:38 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin | 2021-01-17 12:42:54 +0100 |
| commit | e41ee855283b79dfd0734e573e9b8d091070190b (patch) | |
| tree | f04368824e89a9cc9cea81ed42cedf0d16d86498 /hw/acpi | |
| parent | acpi: Fix unmatched expected DSDT.pxb file (diff) | |
| download | qemu-e41ee855283b79dfd0734e573e9b8d091070190b.tar.gz qemu-e41ee855283b79dfd0734e573e9b8d091070190b.tar.xz qemu-e41ee855283b79dfd0734e573e9b8d091070190b.zip | |
acpi: Add addr offset in build_crs
AML needs Address Translation offset to describe how a bridge translates
addresses accross the bridge when using an address descriptor, and
especially on ARM, the translation offset of pio resource is usually
non zero.
Therefore, it's necessary to pass offset for pio, mmio32, mmio64 and bus
number into build_crs.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Message-Id: <20210114100643.10617-4-cenjiahui@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/acpi')
| -rw-r--r-- | hw/acpi/aml-build.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index f976aa667b..7b6ebb0cc8 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2076,7 +2076,9 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL, NULL); } -Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, + uint32_t mmio32_offset, uint64_t mmio64_offset, + uint16_t bus_nr_offset) { Aml *crs = aml_resource_template(); CrsRangeSet temp_range_set; @@ -2189,10 +2191,10 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) for (i = 0; i < temp_range_set.io_ranges->len; i++) { entry = g_ptr_array_index(temp_range_set.io_ranges, i); aml_append(crs, - aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, - AML_POS_DECODE, AML_ENTIRE_RANGE, - 0, entry->base, entry->limit, 0, - entry->limit - entry->base + 1)); + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0, entry->base, entry->limit, io_offset, + entry->limit - entry->base + 1)); crs_range_insert(range_set->io_ranges, entry->base, entry->limit); } @@ -2205,7 +2207,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, - 0, entry->base, entry->limit, 0, + 0, entry->base, entry->limit, mmio32_offset, entry->limit - entry->base + 1)); crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); } @@ -2217,7 +2219,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, - 0, entry->base, entry->limit, 0, + 0, entry->base, entry->limit, mmio64_offset, entry->limit - entry->base + 1)); crs_range_insert(range_set->mem_64bit_ranges, entry->base, entry->limit); @@ -2230,7 +2232,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 0, pci_bus_num(host->bus), max_bus, - 0, + bus_nr_offset, max_bus - pci_bus_num(host->bus) + 1)); return crs; |