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| author | Peter Maydell | 2022-07-18 17:29:32 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-07-18 17:29:32 +0200 |
| commit | 782378973121addeb11b13fd12a6ac2e69faa33f (patch) | |
| tree | dbb9f368e6e40347dd41d0a981ac533409e7dae7 /hw/adc/npcm7xx_adc.c | |
| parent | Merge tag 'qga-win32-pull-2022-07-18' of github.com:kostyanf14/qemu into staging (diff) | |
| parent | Align Raspberry Pi DMA interrupts with Linux DTS (diff) | |
| download | qemu-782378973121addeb11b13fd12a6ac2e69faa33f.tar.gz qemu-782378973121addeb11b13fd12a6ac2e69faa33f.tar.xz qemu-782378973121addeb11b13fd12a6ac2e69faa33f.zip | |
Merge tag 'pull-target-arm-20220718' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high
* target/arm: Fill in VL for tbflags when SME enabled and SVE disabled
* target/arm: Fix aarch64_sve_change_el for SME
* linux-user/aarch64: Do not clear PROT_MTE on mprotect
* target/arm: Honour VTCR_EL2 bits in Secure EL2
* hw/adc: Fix CONV bit in NPCM7XX ADC CON register
* hw/adc: Make adci[*] R/W in NPCM7XX ADC
* target/arm: Don't set syndrome ISS for loads and stores with writeback
* Align Raspberry Pi DMA interrupts with Linux DTS
# gpg: Signature made Mon 18 Jul 2022 14:58:26 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20220718' of https://git.linaro.org/people/pmaydell/qemu-arm:
Align Raspberry Pi DMA interrupts with Linux DTS
target/arm: Don't set syndrome ISS for loads and stores with writeback
hw/adc: Make adci[*] R/W in NPCM7XX ADC
hw/adc: Fix CONV bit in NPCM7XX ADC CON register
target/arm: Honour VTCR_EL2 bits in Secure EL2
target/arm: Store TCR_EL* registers as uint64_t
target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t
target/arm: Fix big-endian host handling of VTCR
target/arm: Fold regime_tcr() and regime_tcr_value() together
target/arm: Calculate mask/base_mask in get_level1_table_address()
target/arm: Define and use new regime_tcr_value() function
linux-user/aarch64: Do not clear PROT_MTE on mprotect
target/arm: Fix aarch64_sve_change_el for SME
target/arm: Fill in VL for tbflags when SME enabled and SVE disabled
hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/adc/npcm7xx_adc.c')
| -rw-r--r-- | hw/adc/npcm7xx_adc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c index 0f0a9f63e2..bc6f3f55e6 100644 --- a/hw/adc/npcm7xx_adc.c +++ b/hw/adc/npcm7xx_adc.c @@ -36,7 +36,7 @@ REG32(NPCM7XX_ADC_DATA, 0x4) #define NPCM7XX_ADC_CON_INT BIT(18) #define NPCM7XX_ADC_CON_EN BIT(17) #define NPCM7XX_ADC_CON_RST BIT(16) -#define NPCM7XX_ADC_CON_CONV BIT(14) +#define NPCM7XX_ADC_CON_CONV BIT(13) #define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8) #define NPCM7XX_ADC_MAX_RESULT 1023 @@ -242,7 +242,7 @@ static void npcm7xx_adc_init(Object *obj) for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) { object_property_add_uint32_ptr(obj, "adci[*]", - &s->adci[i], OBJ_PROP_FLAG_WRITE); + &s->adci[i], OBJ_PROP_FLAG_READWRITE); } object_property_add_uint32_ptr(obj, "vref", &s->vref, OBJ_PROP_FLAG_WRITE); |