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| author | Peter Maydell | 2022-07-14 15:23:03 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-07-18 14:20:14 +0200 |
| commit | f04383e74926180cc56809ec8319115e4cea32b7 (patch) | |
| tree | bb44dd60a8585a18fd45589363a409d626a92719 /hw/adc/stm32f2xx_adc.c | |
| parent | target/arm: Store TCR_EL* registers as uint64_t (diff) | |
| download | qemu-f04383e74926180cc56809ec8319115e4cea32b7.tar.gz qemu-f04383e74926180cc56809ec8319115e4cea32b7.tar.xz qemu-f04383e74926180cc56809ec8319115e4cea32b7.zip | |
target/arm: Honour VTCR_EL2 bits in Secure EL2
In regime_tcr() we return the appropriate TCR register for the
translation regime. For Secure EL2, we return the VSTCR_EL2 value,
but in this translation regime some fields that control behaviour are
in VTCR_EL2. When this code was originally written (as the comment
notes), QEMU didn't care about any of those fields, but we have since
added support for features such as LPA2 which do need the values from
those fields.
Synthesize a TCR value by merging in the relevant VTCR_EL2 fields to
the VSTCR_EL2 value.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1103
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220714132303.1287193-8-peter.maydell@linaro.org
Diffstat (limited to 'hw/adc/stm32f2xx_adc.c')
0 files changed, 0 insertions, 0 deletions