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| author | Igor Mammedov | 2012-07-23 15:22:27 +0200 |
|---|---|---|
| committer | Anthony Liguori | 2012-08-01 15:45:06 +0200 |
| commit | dd673288a8ff73ad77fcc1c255486d2466a772e1 (patch) | |
| tree | 57efd58332d97309c098f7862c44bb947aa73d98 /hw/apic.h | |
| parent | fix Xen compilation (diff) | |
| download | qemu-dd673288a8ff73ad77fcc1c255486d2466a772e1.tar.gz qemu-dd673288a8ff73ad77fcc1c255486d2466a772e1.tar.xz qemu-dd673288a8ff73ad77fcc1c255486d2466a772e1.zip | |
target-i386: move cpu halted decision into x86_cpu_reset
MP initialization protocol differs between cpu families, and for P6 and
onward models it is up to CPU to decide if it will be BSP using this
protocol, so try to model this. However there is no point in implementing
MP initialization protocol in qemu. Thus first CPU is always marked as BSP.
This patch:
- moves decision to designate BSP from board into cpu, making cpu
self-sufficient in this regard. Later it will allow to cleanup hw/pc.c
and remove cpu_reset and wrappers from there.
- stores flag that CPU is BSP in IA32_APIC_BASE to model behavior
described in Inted SDM vol 3a part 1 chapter 8.4.1
- uses MSR_IA32_APICBASE_BSP flag in apic_base for checking if cpu is BSP
patch is based on Jan Kiszka's proposal:
http://thread.gmane.org/gmane.comp.emulators.qemu/100806
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/apic.h')
| -rw-r--r-- | hw/apic.h | 5 |
1 files changed, 4 insertions, 1 deletions
@@ -21,9 +21,12 @@ void apic_sipi(DeviceState *s); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, TPRAccess access); void apic_poll_irq(DeviceState *d); +void apic_designate_bsp(DeviceState *d); /* pc.c */ -int cpu_is_bsp(CPUX86State *env); DeviceState *cpu_get_current_apic(void); +/* cpu.c */ +bool cpu_is_bsp(X86CPU *cpu); + #endif |