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| author | Niek Linnenbank | 2020-03-11 23:18:39 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-03-12 17:27:33 +0100 |
| commit | fef06c8b1b2ea786e660f0c694dc88d052cde33c (patch) | |
| tree | 8e5992f04bb21ab31ea4dcaf8cddca5e73ba31db /hw/arm/allwinner-h3.c | |
| parent | hw/arm: add Xunlong Orange Pi PC machine (diff) | |
| download | qemu-fef06c8b1b2ea786e660f0c694dc88d052cde33c.tar.gz qemu-fef06c8b1b2ea786e660f0c694dc88d052cde33c.tar.xz qemu-fef06c8b1b2ea786e660f0c694dc88d052cde33c.zip | |
hw/arm/allwinner-h3: add Clock Control Unit
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/allwinner-h3.c')
| -rw-r--r-- | hw/arm/allwinner-h3.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 7958f37685..1fff3c317b 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -36,6 +36,7 @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_SRAM_A1] = 0x00000000, [AW_H3_SRAM_A2] = 0x00044000, [AW_H3_SRAM_C] = 0x00010000, + [AW_H3_CCU] = 0x01c20000, [AW_H3_PIT] = 0x01c20c00, [AW_H3_UART0] = 0x01c28000, [AW_H3_UART1] = 0x01c28400, @@ -77,7 +78,6 @@ struct AwH3Unimplemented { { "usb2-phy", 0x01c1c000, 4 * KiB }, { "usb3-phy", 0x01c1d000, 4 * KiB }, { "smc", 0x01c1e000, 4 * KiB }, - { "ccu", 0x01c20000, 1 * KiB }, { "pio", 0x01c20800, 1 * KiB }, { "owa", 0x01c21000, 1 * KiB }, { "pwm", 0x01c21400, 1 * KiB }, @@ -172,6 +172,9 @@ static void allwinner_h3_init(Object *obj) "clk0-freq", &error_abort); object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), "clk1-freq", &error_abort); + + sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), + TYPE_AW_H3_CCU); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -277,6 +280,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C], &s->sram_c); + /* Clock Control Unit */ + qdev_init_nofail(DEVICE(&s->ccu)); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); + /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), |