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| author | Peter Maydell | 2017-09-04 18:21:24 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-09-04 18:21:24 +0200 |
| commit | 2b483739791b33c46e6084b51edcf62107058ae1 (patch) | |
| tree | fab8d4164ff9c0a73fdaad41ee06815d6163e504 /hw/arm/armv7m.c | |
| parent | Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' in... (diff) | |
| parent | arm_gicv3_kvm: Fix compile warning (diff) | |
| download | qemu-2b483739791b33c46e6084b51edcf62107058ae1.tar.gz qemu-2b483739791b33c46e6084b51edcf62107058ae1.tar.xz qemu-2b483739791b33c46e6084b51edcf62107058ae1.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170904-2' into staging
target-arm:
* collection of M profile cleanups and minor bugfixes
* loader: handle ELF files with overlapping zero-init data
* virt: allow PMU instantiation with userspace irqchip
* wdt_aspeed: Add support for the reset width register
* cpu: Define new cpu_transaction_failed() hook
* Mark some SoC devices as not user-creatable
* arm: Fix aa64 ldp register writeback
* arm_gicv3_kvm: Fix compile warning
# gpg: Signature made Mon 04 Sep 2017 17:20:40 BST
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# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
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* remotes/pmaydell/tags/pull-target-arm-20170904-2: (33 commits)
arm_gicv3_kvm: Fix compile warning
target/arm: Fix aa64 ldp register writeback
hw/arm/digic: Mark device with user_creatable = false
hw/arm/aspeed_soc: Mark devices as user_creatable = false
target/arm: Allow deliver_fault() caller to specify EA bit
target/arm: Factor out fault delivery code
cputlb: Support generating CPU exceptions on memory transaction failures
cpu: Define new cpu_transaction_failed() hook
memory.h: Move MemTxResult type to memattrs.h
aspeed_soc: Propagate silicon-rev to watchdog
watchdog: wdt_aspeed: Add support for the reset width register
target/arm/kvm: pmu: improve error handling
hw/arm/virt: allow pmu instantiation with userspace irqchip
target/arm/kvm: pmu: split init and set-irq stages
hw/arm/virt: add pmu interrupt state
hw/arm: use defined type name instead of hard-coded string
loader: Ignore zero-sized ELF segments
loader: Handle ELF files with overlapping zero-initialized data
nvic: Implement "user accesses BusFault" SCS region behaviour
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/armv7m.c')
| -rw-r--r-- | hw/arm/armv7m.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index c8a11f2b53..d2477e84e4 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -146,7 +146,7 @@ static void armv7m_instance_init(Object *obj) &error_abort); memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX); - object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic"); + object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC); qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default()); object_property_add_alias(obj, "num-irq", OBJECT(&s->nvic), "num-irq", &error_abort); @@ -293,7 +293,7 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, cpu_model = "cortex-m3"; } - armv7m = qdev_create(NULL, "armv7m"); + armv7m = qdev_create(NULL, TYPE_ARMV7M); qdev_prop_set_uint32(armv7m, "num-irq", num_irq); qdev_prop_set_string(armv7m, "cpu-model", cpu_model); object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()), |