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authorCédric Le Goater2017-06-02 12:51:49 +0200
committerPeter Maydell2017-06-02 12:51:49 +0200
commit4960f084cfb4d42bb8995dd23ccad168c3e4ad3a (patch)
tree1be9bb56884e8f3b5d0ce6f56220eb8b8ce7c0ee /hw/arm/aspeed.c
parentaspeed/i2c: handle LAST command under the RX command (diff)
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aspeed/i2c: introduce a state machine
The Aspeed I2C controller maintains a state machine in the command register, which is mostly used for debug. Let's start adding a few states to handle abnormal STOP commands. Today, the model uses the busy status of the bus as a condition to do so but it is not precise enough. Also remove the ABNORMAL bit for failing TX commands. This is incorrect with respect to the specs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1494827476-1487-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/aspeed.c')
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