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| author | Cédric Le Goater | 2019-09-04 09:05:01 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-09-13 17:05:01 +0200 |
| commit | c4e1f0b48322a9bc98c37f8413553cb6131daafe (patch) | |
| tree | 20da26dc3f7afd9678620282d69f2c736f7de00d /hw/arm/aspeed.c | |
| parent | aspeed: Use consistent typenames (diff) | |
| download | qemu-c4e1f0b48322a9bc98c37f8413553cb6131daafe.tar.gz qemu-c4e1f0b48322a9bc98c37f8413553cb6131daafe.tar.xz qemu-c4e1f0b48322a9bc98c37f8413553cb6131daafe.zip | |
aspeed/smc: Add support for DMAs
The FMC controller on the Aspeed SoCs support DMA to access the flash
modules. It can operate in a normal mode, to copy to or from the flash
module mapping window, or in a checksum calculation mode, to evaluate
the best clock settings for reads.
The model introduces two custom address spaces for DMAs: one for the
AHB window of the FMC flash devices and one for the DRAM. The latter
is populated using a "dram" link set from the machine with the RAM
container region.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190904070506.1052-6-clg@kaod.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/aspeed.c')
| -rw-r--r-- | hw/arm/aspeed.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 13e208c78c..aa72be309d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -190,6 +190,8 @@ static void aspeed_board_init(MachineState *machine, &error_abort); object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", &error_abort); + object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container), + "dram", &error_abort); if (machine->kernel_filename) { /* * When booting with a -kernel command line there is no u-boot |