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| author | Peter Crosthwaite | 2013-12-17 20:42:29 +0100 |
|---|---|---|
| committer | Peter Maydell | 2013-12-17 20:42:29 +0100 |
| commit | e2cddeeb97a47cd58384cfd86ae79c9bbe829255 (patch) | |
| tree | 8f2a1582c052c7ba23a7fe49bc59eb978478bd39 /hw/arm/highbank.c | |
| parent | arm/xilinx_zynq: Implement CBAR initialisation (diff) | |
| download | qemu-e2cddeeb97a47cd58384cfd86ae79c9bbe829255.tar.gz qemu-e2cddeeb97a47cd58384cfd86ae79c9bbe829255.tar.xz qemu-e2cddeeb97a47cd58384cfd86ae79c9bbe829255.zip | |
arm/highbank.c: Fix MPCore periphbase name
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 90798bd3507205c16238b8b19a1a58c5437cf7ca.1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/highbank.c')
| -rw-r--r-- | hw/arm/highbank.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index cb32325082..c75b425c01 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -28,11 +28,11 @@ #include "exec/address-spaces.h" #include "qemu/error-report.h" -#define SMP_BOOT_ADDR 0x100 -#define SMP_BOOT_REG 0x40 -#define GIC_BASE_ADDR 0xfff10000 +#define SMP_BOOT_ADDR 0x100 +#define SMP_BOOT_REG 0x40 +#define MPCORE_PERIPHBASE 0xfff10000 -#define NIRQ_GIC 160 +#define NIRQ_GIC 160 /* Board init. */ @@ -55,7 +55,7 @@ static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 0xe1110001, /* tst r1, r1 */ 0x0afffffb, /* beq <wfi> */ 0xe12fff11, /* bx r1 */ - GIC_BASE_ADDR /* privbase: gic address. */ + MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ }; for (n = 0; n < ARRAY_SIZE(smpboot); n++) { smpboot[n] = tswap32(smpboot[n]); @@ -236,7 +236,8 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine) cpu = ARM_CPU(object_new(object_class_get_name(oc))); - object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err); + object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", + &err); if (err) { error_report("%s", error_get_pretty(err)); exit(1); @@ -287,7 +288,7 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine) qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); - sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR); + sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } |