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| author | Philippe Mathieu-Daudé | 2020-05-04 09:28:21 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-05-11 12:05:52 +0200 |
| commit | 27d6dea3d702b4f9cefacfc8438a9478c03092e4 (patch) | |
| tree | a8b2a2aed46997ef9631814bebf364ff4d182896 /hw/arm/nrf51_soc.c | |
| parent | hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition (diff) | |
| download | qemu-27d6dea3d702b4f9cefacfc8438a9478c03092e4.tar.gz qemu-27d6dea3d702b4f9cefacfc8438a9478c03092e4.tar.xz qemu-27d6dea3d702b4f9cefacfc8438a9478c03092e4.zip | |
hw/timer/nrf51_timer: Display timer ID in trace events
The NRF51 series SoC have 3 timer peripherals, each having
4 counters. To help differentiate which peripheral is accessed,
display the timer ID in the trace events.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200504072822.18799-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/nrf51_soc.c')
| -rw-r--r-- | hw/arm/nrf51_soc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index e50473fd19..71309e53cc 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -150,6 +150,11 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) /* TIMER */ for (i = 0; i < NRF51_NUM_TIMERS; i++) { + object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); if (err) { error_propagate(errp, err); |