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authorFabian Aggeler2014-12-11 13:07:51 +0100
committerPeter Maydell2014-12-11 13:07:51 +0100
commit0c17d68c1d3d6c35f37f5692042d2edb65c8bcc0 (patch)
tree77e77723897d5c5d0eb112931cd3f85feb86c3ad /hw/arm/pxa2xx.c
parenttarget-arm: make TTBCR banked (diff)
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target-arm: make DACR banked
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-19-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/pxa2xx.c')
-rw-r--r--hw/arm/pxa2xx.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 2b00b598ca..8967cc4e0b 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -276,7 +276,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
s->cpu->env.cp15.sctlr_ns = 0;
s->cpu->env.cp15.c1_coproc = 0;
s->cpu->env.cp15.ttbr0_el[1] = 0;
- s->cpu->env.cp15.c3 = 0;
+ s->cpu->env.cp15.dacr_ns = 0;
s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */