diff options
| author | Fabian Aggeler | 2014-12-11 13:07:51 +0100 |
|---|---|---|
| committer | Peter Maydell | 2014-12-11 13:07:51 +0100 |
| commit | 7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc (patch) | |
| tree | 318c5e217510ab0c8a198c9fc3335024a3f6ca00 /hw/arm/pxa2xx.c | |
| parent | target-arm: make CSSELR banked (diff) | |
| download | qemu-7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc.tar.gz qemu-7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc.tar.xz qemu-7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc.zip | |
target-arm: make TTBR0/1 banked
Adds secure and non-secure bank register suport for TTBR0 and TTBR1.
Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as
well as a CP register definition for TTBR0_EL3. Added a union containing
both EL based array fields and secure and non-secure fields mapped to them.
Updated accesses to use A32_BANKED_CURRENT_REG_GET macro.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-17-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/pxa2xx.c')
| -rw-r--r-- | hw/arm/pxa2xx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 11d51afcf9..2b00b598ca 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -275,7 +275,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; s->cpu->env.cp15.sctlr_ns = 0; s->cpu->env.cp15.c1_coproc = 0; - s->cpu->env.cp15.ttbr0_el1 = 0; + s->cpu->env.cp15.ttbr0_el[1] = 0; s->cpu->env.cp15.c3 = 0; s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |