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| author | Peter Maydell | 2017-09-07 14:54:54 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-09-07 14:54:54 +0200 |
| commit | 4672cbd7bed88dc67f089e84a0fd5d7739020c92 (patch) | |
| tree | 5966c04f666e89c49a1de7d58552824da2dc4e90 /hw/arm/sabrelite.c | |
| parent | boards.h: Define new flag ignore_memory_transaction_failures (diff) | |
| download | qemu-4672cbd7bed88dc67f089e84a0fd5d7739020c92.tar.gz qemu-4672cbd7bed88dc67f089e84a0fd5d7739020c92.tar.xz qemu-4672cbd7bed88dc67f089e84a0fd5d7739020c92.zip | |
hw/arm: Set ignore_memory_transaction_failures for most ARM boards
Set the MachineClass flag ignore_memory_transaction_failures
for almost all ARM boards. This means they retain the legacy
behaviour that accesses to unimplemented addresses will RAZ/WI
rather than aborting, when a subsequent commit adds support
for external aborts.
The exceptions are:
* virt -- we know that guests won't try to prod devices
that we don't describe in the device tree or ACPI tables
* mps2 -- this board was written to use unimplemented-device
for all the ranges with devices we don't yet handle
New boards should not set the flag, but instead be written
like the mps2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1504626814-23124-3-git-send-email-peter.maydell@linaro.org
For the Xilinx boards:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'hw/arm/sabrelite.c')
| -rw-r--r-- | hw/arm/sabrelite.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 4e7ac8cc4f..ee140e5d9e 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -122,6 +122,7 @@ static void sabrelite_machine_init(MachineClass *mc) mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)"; mc->init = sabrelite_init; mc->max_cpus = FSL_IMX6_NUM_CPUS; + mc->ignore_memory_transaction_failures = true; } DEFINE_MACHINE("sabrelite", sabrelite_machine_init) |