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| author | Eric Auger | 2020-07-28 17:08:14 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-08-24 11:02:06 +0200 |
| commit | e7c3b9d9a0ddee7daa9b08bd14bd3ebbcf5f5cd3 (patch) | |
| tree | 19bee6a1f3e39fb38bce6cdefeb934162b8075fc /hw/arm/smmuv3-internal.h | |
| parent | hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support (diff) | |
| download | qemu-e7c3b9d9a0ddee7daa9b08bd14bd3ebbcf5f5cd3.tar.gz qemu-e7c3b9d9a0ddee7daa9b08bd14bd3ebbcf5f5cd3.tar.xz qemu-e7c3b9d9a0ddee7daa9b08bd14bd3ebbcf5f5cd3.zip | |
hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support
HAD is a mandatory features with SMMUv3.1 if S1P is set, which is
our case. Other 3.1 mandatory features come with S2P which we don't
have.
So let's support HAD and advertise SMMUv3.1 support in AIDR.
HAD support allows the CD to disable hierarchical attributes, ie.
if the HAD0/1 bit is set, the APTable field of table descriptors
walked through TTB0/1 is ignored.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-11-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/smmuv3-internal.h')
| -rw-r--r-- | hw/arm/smmuv3-internal.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index bd34a4f330..9ae7d97faf 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -54,6 +54,7 @@ REG32(IDR1, 0x4) REG32(IDR2, 0x8) REG32(IDR3, 0xc) + FIELD(IDR3, HAD, 2, 1); REG32(IDR4, 0x10) REG32(IDR5, 0x14) FIELD(IDR5, OAS, 0, 3); @@ -578,6 +579,7 @@ static inline int pa_range(STE *ste) lo = (x)->word[(sel) * 2 + 2] & ~0xfULL; \ hi | lo; \ }) +#define CD_HAD(x, sel) extract32((x)->word[(sel) * 2 + 2], 1, 1) #define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6) #define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2) |