diff options
| author | Peter Maydell | 2019-05-24 14:48:29 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-06-13 16:14:03 +0200 |
| commit | 97fb318d37be4d21125e89c96e4e92ea33beac51 (patch) | |
| tree | 68e4701de052865806211c25c3cc2a443e39aaae /hw/arm/smmuv3.c | |
| parent | target/arm: Implement NSACR gating of floating point (diff) | |
| download | qemu-97fb318d37be4d21125e89c96e4e92ea33beac51.tar.gz qemu-97fb318d37be4d21125e89c96e4e92ea33beac51.tar.xz qemu-97fb318d37be4d21125e89c96e4e92ea33beac51.zip | |
hw/arm/smmuv3: Fix decoding of ID register range
The SMMUv3 ID registers cover an area 0x30 bytes in size
(12 registers, 4 bytes each). We were incorrectly decoding
only the first 0x20 bytes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20190524124829.2589-1-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm/smmuv3.c')
| -rw-r--r-- | hw/arm/smmuv3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index fd8ec7860e..e96d5beb9a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1232,7 +1232,7 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { switch (offset) { - case A_IDREGS ... A_IDREGS + 0x1f: + case A_IDREGS ... A_IDREGS + 0x2f: *data = smmuv3_idreg(offset - A_IDREGS); return MEMTX_OK; case A_IDR0 ... A_IDR5: |