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| author | Peter Maydell | 2021-02-19 15:46:07 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-08 18:20:03 +0100 |
| commit | 4668b441cb667619916d4bc6a204f3df06730dfb (patch) | |
| tree | 36bea8a85984bb1c4c58c8d3be76a695d768e993 /hw/arm/xlnx-zcu102.c | |
| parent | hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo (diff) | |
| download | qemu-4668b441cb667619916d4bc6a204f3df06730dfb.tar.gz qemu-4668b441cb667619916d4bc6a204f3df06730dfb.tar.xz qemu-4668b441cb667619916d4bc6a204f3df06730dfb.zip | |
hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block
Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register
block. Because this block is per-CPU and does not clash with any of the
SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the
existing has_cachectrl, has_cpusectrl and has_cpuid, rather than
trying to add per-CPU-device support to the devinfo array handling code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-35-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm/xlnx-zcu102.c')
0 files changed, 0 insertions, 0 deletions