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authorEdgar E. Iglesias2022-03-16 17:46:43 +0100
committerPeter Maydell2022-03-18 12:31:20 +0100
commit63320bcaed89642044500ec017c0acb592220831 (patch)
treef8080adddfb1a2751ed1f05e8adabd4375fe081e /hw/arm/xlnx-zynqmp.c
parenthw/misc: Add a model of the Xilinx ZynqMP CRF (diff)
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hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
Connect the ZynqMP CRF - Clock Reset FPD device. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-5-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/xlnx-zynqmp.c')
-rw-r--r--hw/arm/xlnx-zynqmp.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 47324cdc44..f4575eea7f 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -52,6 +52,9 @@
#define QSPI_DMA_ADDR 0xff0f0800
#define NUM_QSPI_IRQ_LINES 2
+#define CRF_ADDR 0xfd1a0000
+#define CRF_IRQ 120
+
/* Serializer/Deserializer. */
#define SERDES_ADDR 0xfd400000
#define SERDES_SIZE 0x20000
@@ -280,6 +283,18 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
}
+static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+
+ object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF);
+ sbd = SYS_BUS_DEVICE(&s->crf);
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, CRF_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
+}
+
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
{
static const struct UnimpInfo {
@@ -684,6 +699,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
xlnx_zynqmp_create_bbram(s, gic_spi);
xlnx_zynqmp_create_efuse(s, gic_spi);
+ xlnx_zynqmp_create_crf(s, gic_spi);
xlnx_zynqmp_create_unimp_mmio(s);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {