diff options
author | Peter Maydell | 2019-05-23 15:47:44 +0200 |
---|---|---|
committer | Peter Maydell | 2019-05-23 15:47:44 +0200 |
commit | 09380dd131eadf31a7ff286e766892b9a1ec6e31 (patch) | |
tree | 6ada3ff7c37630b50551a7051a875608941ce914 /hw/arm | |
parent | hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1} (diff) | |
download | qemu-09380dd131eadf31a7ff286e766892b9a1ec6e31.tar.gz qemu-09380dd131eadf31a7ff286e766892b9a1ec6e31.tar.xz qemu-09380dd131eadf31a7ff286e766892b9a1ec6e31.zip |
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
The ICC_CTLR_EL3 register includes some bits which are aliases
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
Unfortunately a missing '~' in the code to update the bits
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
the ICC_CLTR_EL1 register values.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm')
0 files changed, 0 insertions, 0 deletions