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author | Peter Maydell | 2019-02-28 11:55:16 +0100 |
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committer | Peter Maydell | 2019-02-28 12:03:04 +0100 |
commit | 0f862986e02f5cc188e56b8bd6a8a203091c1dc2 (patch) | |
tree | 9772e873d653d2cf1d7ef24ff8e377128d62f632 /hw/arm | |
parent | hw/arm/iotkit-sysctl: Add SSE-200 registers (diff) | |
download | qemu-0f862986e02f5cc188e56b8bd6a8a203091c1dc2.tar.gz qemu-0f862986e02f5cc188e56b8bd6a8a203091c1dc2.tar.xz qemu-0f862986e02f5cc188e56b8bd6a8a203091c1dc2.zip |
hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
The CPUWAIT register acts as a sort of power-control: if a bit
in it is 1 then the CPU will have been forced into waiting
when the system was reset (which in QEMU we model as the
CPU starting powered off). Writing a 0 to the register will
allow the CPU to boot (for QEMU, we model this as powering
it on). Note that writing 0 to the register does not power
off a CPU.
For this to work correctly we need to also honour the
INITSVTOR* registers, which let the guest control where the
CPU will load its SP and PC from when it comes out of reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-8-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm')
0 files changed, 0 insertions, 0 deletions