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| author | Peter Maydell | 2019-02-01 15:55:41 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-02-01 15:55:41 +0100 |
| commit | 3693f217d38f053fa5a7fcd2841c07926c026218 (patch) | |
| tree | 6b871f3400bc5ca86da8931abc95035424a63b5d /hw/arm | |
| parent | hw/arm/nrf51_soc: set object owner in memory_region_init_ram (diff) | |
| download | qemu-3693f217d38f053fa5a7fcd2841c07926c026218.tar.gz qemu-3693f217d38f053fa5a7fcd2841c07926c026218.tar.xz qemu-3693f217d38f053fa5a7fcd2841c07926c026218.zip | |
armv7m: Don't assume the NVIC's CPU is CPU 0
Currently the ARMv7M NVIC object's realize method assumes that the
CPU the NVIC is attached to is CPU 0, because it thinks there can
only ever be one CPU in the system. To allow a dual-Cortex-M33
setup we need to remove this assumption; instead the armv7m
wrapper object tells the NVIC its CPU, in the same way that it
already tells the CPU what the NVIC is.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-2-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/armv7m.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index f444652830..f9aa83d20e 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -178,10 +178,12 @@ static void armv7m_realize(DeviceState *dev, Error **errp) } } - /* Tell the CPU where the NVIC is; it will fail realize if it doesn't - * have one. + /* + * Tell the CPU where the NVIC is; it will fail realize if it doesn't + * have one. Similarly, tell the NVIC where its CPU is. */ s->cpu->env.nvic = &s->nvic; + s->nvic.cpu = s->cpu; object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); if (err != NULL) { |