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| author | Peter Maydell | 2019-02-15 10:56:39 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-02-15 10:56:39 +0100 |
| commit | 5007c904e158aaaf97e65338e52f5ef9e8df0944 (patch) | |
| tree | ab90266c344f9460be2bd424661cf991ba6dcfe9 /hw/arm | |
| parent | hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 (diff) | |
| download | qemu-5007c904e158aaaf97e65338e52f5ef9e8df0944.tar.gz qemu-5007c904e158aaaf97e65338e52f5ef9e8df0944.tar.xz qemu-5007c904e158aaaf97e65338e52f5ef9e8df0944.zip | |
hw/arm/armsse: Fix miswiring of expansion IRQs
In commit 91c1e9fcbd7548db368 where we added dual-CPU support to
the ARMSSE, we set up the wiring of the expansion IRQs via nested
loops: the outer loop on 'i' loops for each CPU, and the inner loop
on 'j' loops for each interrupt. Fix a typo which meant we were
wiring every expansion IRQ line to external IRQ 0 on CPU 0 and
to external IRQ 1 on CPU 1.
Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/armsse.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 5d53071a5a..9a8c49547d 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -565,7 +565,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); for (j = 0; j < s->exp_numirq; j++) { - s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, i + 32); + s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); } if (i == 0) { gpioname = g_strdup("EXP_IRQ"); |