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| author | Peter Maydell | 2021-02-19 15:46:12 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-08 18:20:03 +0100 |
| commit | 6ac80818941829c01363e9feeefe08e8bc693ab7 (patch) | |
| tree | 2bea086b7cf05b7bb1e04350f27f3c34420aea9d /hw/arm | |
| parent | hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register (diff) | |
| download | qemu-6ac80818941829c01363e9feeefe08e8bc693ab7.tar.gz qemu-6ac80818941829c01363e9feeefe08e8bc693ab7.tar.xz qemu-6ac80818941829c01363e9feeefe08e8bc693ab7.zip | |
hw/misc/mps2-scc: Implement changes for AN547
Implement the minor changes required to the SCC block for AN547 images:
* CFG2 and CFG5 exist (like AN524)
* CFG3 is reserved (like AN524)
* CFG0 bit 1 is CPU_WAIT; we don't implement it, but note this
in the TODO comment
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-40-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm')
0 files changed, 0 insertions, 0 deletions